Semiconductor Sector Service Bureau

Talent

Digital IC Design Concepts & Tools Training 2026

11th Aug 2026

Online Short Course

This short course provides a comprehensive, hands-on journey through the Digital IC Design flow from high-level RTL design to physical layout (GDSII).

Applications ARE NOW open – CLICK HERE TO APPLY

Participants will learn the key stages of the Digital IC Design flow, including RTL Design, Synthesis, Static Timing Analysis, Floorplanning, Placement, Routing, and Signoff, using the open-source EDA toolchain (OpenROAD). By the end of the course, participants will gain hands-on experience in RTL Synthesis and Digital Implementation, reinforcing their understanding of the complete Digital IC Design flow.
All course materials are the intellectual property of Professor Omid Kavehei, The University of Sydney.

Objectives:

  • To equip the next generation of chip design engineers with the skills required for Digital IC Design in Australia.
  • To help participants learn chip design from an industry perspective.
  • To inspire current engineering students to pursue careers in chip design.

Learning Outcomes:

  • Understand the complete Digital IC Design flow from RTL to GDSII.

Target Audience: 

  • This course is open to Undergraduate and Postgraduate students, as well as industry professionals in Australia seeking to upskill in Digital IC Design.

Required Knowledge:

  • Basic background in Electronics or Computer Engineering, including fundamental VLSI concepts.

Topics Covered:

  • Introduction to Semiconductors
  • Digital IC Design
  • RTL Design
  • Static Timing Analysis
  • RTL Synthesis
  • Digital implementation
  • Low power design

Applications:

Applications are open to students and professionals residing in Australia. Applicants are required to complete the application form. The form includes basic questions about your existing knowledge in IC Design and asks for a CV demonstrating your experience to date.

Fee:

A subsidised fee of $70 will be payable upon acceptance into the short course. Further subsidised places will be available for successful applicants upon request and an assessment of personal circumstances.

Class dates:

This is an 8 week course with 2 sessions per week on Wednesdays 6.00pm – 8.30pm and Saturdays 10am – 12.30pm. Sessions will be delivered via Zoom on the below dates:

14 October 2026, 17 October 2026, 21 October 2026,  24 October 2026, 30 October 2026, 31 October 2026, 4 November 2026, 7 November 2026, 11 November 2026, 14 November 2026, 18 November 2026, 21 November 2026, 25 November 2026, 28 November 2026, 2 December 2026, 5 December 2026.

Timeline:

  • Applications are open from Thursday 20 August and will close 5.00pm on Thursday 17 September.
  • Successful applicants will be informed by email on Friday 25 September. If you are successful you will have 7 days to accept your position. Failure to do so will result in your place being offered to a shortlisted applicant.
  • Delivery Mode: online, with a Zoom link and Canvas LMS for learning materials.

Hardware requirements:

  • Windows:
    OS: Windows 10/11
    CPU: 4+ cores
    RAM: 16GB
  • Apple:
    OS: macOS 13 or later
    CPU: Apple M1/M2M3
    RAM: 16GB
  • Participants will be required to download a third party tool for labs. Windows is recommended as the preferred OS for this tool.

For any questions regarding the course, please email info@s3b.au


Semiconductor Sector Service Bureau